1. Field of the Invention
This invention relates to microprocessors and more particularly to mechanisms for expanding register address space within an existing microprocessor architecture.
2. Description of the Relevant Art
Microprocessor manufacturers continue to develop new products which execute .times.86 instructions in order to maintain compatibility with the vast amount of software developed for previous 80.times.86 generations--the 8086/8, 80286, 80386, and 80486. Maintaining software compatibility has forced many architectural compromises in newer products. In order to retain the functions of earlier products, hardware has often been simply modified or extended in order to increase capability and performance.
The .times.86 instruction set is relatively complex and is characterized by a plurality of variable byte length instructions. A generic format illustrative of the .times.86 instruction set is shown in FIG. 1. As illustrated in the figure, an .times.86 instruction consists of from one to five optional prefix bytes 102, followed by an operation code (opcode) field 104, an optional addressing mode (Mod R/M) byte 106, an optional scale-index-base (SIB) byte 108, an optional displacement field 110, and an optional immediate data field 112.
The opcode field 104 defines the basic operation for a particular instruction. The default operation of a particular opcode may be modified by one or more prefix bytes. For example, a prefix byte may be used to change the address or operand size for an instruction, to override the default segment used in memory addressing, or to instruct the processor to repeat a string operation a number of times. The opcode field 104 follows the prefix bytes 102, if any, and may be one or two bytes in length. The addressing mode (Mod R/M) byte 106 specifies the registers used as well as memory addressing modes. The scale-index-base (SIB) byte 108 is used only in 32-bit base-relative addressing using scale and index factors. A base field of the SIB byte specifies which register contains the base value for the address calculation and an index field specifies which register contains the index value. A scale field specifies the power of two by which the index value will be multiplied before being added, along with any displacement, to the base value. The next instruction field is the optional displacement field 110, which may be from one to four bytes in length. The displacement field 110 contains a constant used in address calculations. The optional immediate field 112, which may also be from one to four bytes in length, contains a constant used as an instruction operand. The shortest .times.86 instructions are only one byte long, and comprise a single opcode byte. The 80286 sets a maximum length for an instruction at 10 bytes, while the 80386 and 80486 both allow instruction lengths of up to 15 bytes.
FIGS. 2 and 3 illustrate the internal fields associated with the Mod R/M byte and of the SIB byte, respectively. References to a particular register of the .times.86 architecture may appear within the REG/OP or the R/M field of the Mod R/M byte, or within the index field and base field of the SIB byte. (A register address may alternatively be implied by an opcode.) Thus, there are four possible references to a register in an .times.86 instruction (although only three register references may appear in any particular instruction). The REG/OP and R/M fields in the Mod R/M byte can specify the source and destination registers, and the base and index fields in the SIB byte can specify the base and index registers used in operand address calculations for memory accesses.
A significant deficiency of the .times.86 architecture is the small number of general purpose registers. Typical RISC processors have at least thirty-two general purpose registers, as opposed to eight for the .times.86. A larger register set allows more operands to be stored in the faster-access register file, rather than in relatively slow memory. Modern compilers are also able to take advantage of a larger number of registers to expose greater instruction level parallelism for increased superscalar execution performance. In addition to the limited number of .times.86 registers, use of them by the compiler is complicated by the fact that most have special implicit uses in various instructions. Expanding the number of registers would alleviate these limitations.